In present, there are a lot of passive devices in the integrated circuits. One of the most important components in RF CMOS/BiCMOS integrated circuits is on-chip inductor. Inductor has great impact on the RF characteristic in common wireless products. The design and analysis for this component has been widely researched as a result. Nowadays, the high Q on-chip inductor has been widely used in voltage controlled oscillator, low noise amplifier and other RF building blocks. On-chip stacked inductor reduced chip area in a large extent, which reduced the production cost.
Q factor is the major specification of inductor, high Q means low loss and high efficiency.
In traditional logic and RF process, because the thickness of top metal is larger than that of the bottom layers, the parasitic resistance of bottom metal is higher than that of top metal in stacked inductor. Conventional stacked inductor is shown in FIG. 1; the metal width and space are kept the same at different layers, possessing large inductance. However, the parasitic resistance and capacitance lead to decrease of Q factor and Self Resonance Frequency. As a result, it could not meet the requirement of circuit design.